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Description: In house Physical design flow for supporting IP Hardening, Validation on products. Flow supports based on product requirements for advanced nodes like 3nm, 5nm etc (including various foundry process). The internship also includes validation of proteanTecs Implementation solution, in Flow Manager, before release using complex test-designs on advanced nodes

Skill sets: Knowledge in VLSI Design flow (including Physical Design), STA, TCL/Shell basic coding.

Traits expectation: Problem solving, curious, critical thinking, debugging.

Expected learning: Will learn on physical design aspect of chip designing (RTL2GDS), flow methodology, challenges associated with advanced nodes and Industry approach of solving.

Specific courses required for project execution: VLSI flow, small scripting background (for further ramp-up, Training will be provided in house by experts/mentors)

e:T5f0,

ProteanTecs - Physical Design RTL2GDSII

Station Overview

Project 1

Flow Manager (Physical Design RTL2GDS Flow) & Product validation

Project 2

Title: Physical Design RTL2GDS Flow