Description:

Job Description:

As a Physical Design Engineer in the Implementation team, you will contribute to the development of industry-leading CPU IP to support the SiFive vision of enabling chip design by anyone. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

Implementing and optimizing our broad portfolio of RISC-V CPU's from RTL to GDSII.
Closing ambitious performance, power, and area (PPA) goals at block and/or CPU level.
Collaborating with the microarchitecture and RTL teams to optimize PPA tradeoffs.
Contributing to physical implementation flow development to drive best-in-class automation and PPA.
Support the physical design team in block-level or subsystem-level implementation, including synthesis, floor planning, placement, CTS, routing, and signoff. Implement IP using physical design implementation flows from RTL to GDS.
Assist in PPA analysis and reporting to help guide design optimization efforts.
Participate in co-design discussions with cross-functional teams to optimize the design on PPA and other implementation metrics.
Power Analysis Using PTPX:
Assist in running PrimeTime PX (PTPX) for power analysis, including:
Loading design files and activity data (e.g., SAIF/VCD files).
Performing dynamic and static power analysis to identify areas of high power consumption.
Generating and interpreting power reports, focusing on both dynamic and leakage power.
Collaboration:
Work alongside the architecture, RTL, and logic teams to help implement power reduction strategies and validate power estimates.
Develop Power Models:
Assist in creating power models using Python scripts to help estimate power consumption across different design scenarios.
Scripting & Automation:
Write Python, Perl, or Tcl scripts to automate power analysis flows, run simulations, and generate detailed power reports.
Automate flow steps in various EDA tools to improve productivity.
Perform PPA analysis on a series of the modern processors.
Integrate the state-of-the-art process nodes and tool features into existing flow for enhancement.
Construct and maintain a well-defined database to handle the complex dataset systematically.
Cross collaboration with diverse teams worldwide.

Requirements

Ability to work well with others and a belief that engineering is a team sport
Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Detail-oriented with strong problem-solving and communication skills. Eagerness to learn and collaborate in a fast-paced, team-oriented environment.
Good understanding of digital logic design, CMOS fundamentals and Digital VLSI design concepts, digital circuits.
Exposure to industry EDA tools (e.g., Synopsys, Cadence) is a plus. Knowledge of scripting languages like TCL, Python, or Perl is advantageous.
Familiarity with power analysis tools such as PrimeTime PX (PTPX).
Experience with scripting languages (Python, Perl, Tcl) for automation.
Knowledge of low-power design techniques and methodologies.

Preferred Skills:

Familiarity with power analysis tools such as PrimeTime PX (PTPX).
Experience with scripting languages (Python, Perl, Tcl) for automation.
Knowledge of low-power design techniques and methodologies.
Experience in version control system(Git).
Experience in HDL (Verilog, VHDL, SystemVerilog)
Experience in logic, physical, low-power design, PPA analysis of ASIC design.
Experience in using EDA tools on VLSI, such as DC, Genus, FC, Innovus, PT/PTPX, PowerArtist.

Required Skills & Traits:

Expected Outcomes:

Specific courses required for project execution:

SiFive India Pvt Ltd

Station Overview

Project 1

Continuing students

Project 2

Details Awaited

Project 3

Title: Intern, Physical Design