RTL Design Intern – RISC-V System IP

Description:

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.This internship offers the opportunity to work with the System IP Design team focused on implementing IP’s and Sub Systems for RISC-V based High Performance Compute Clusters. The intern will contribute to the microarchitectural definition, Synthesisable RTL design, feature enhancements, and performance improvements of IP’s and Sub Systems. The role also includes IP QC flows, debugging design issues, analysing performance bottlenecks, and collaborating with verification and architecture teams for successful IP delivery.Required Skills & Traits:

Solid understanding of Digital design principles (FSMs, pipelining, data/control path design).

Projects with SystemVerilog/Verilog for RTL design.

Basic awareness of IP Design Flows and practices.

Familiarity with bus protocols (AXI, AHB, APB, CHI, etc.).

Familiarity with RISC-V architecture and ISA extensions.

Scripting skills (Python, TCL, or Makefiles) to support automation of build and design tasks.

Familiarity with version control systems like Git.

Good analytical, problem-solving and debugging skills, willingness to ask technical questions, and ability to learn independently.

Expected Outcomes:

Design and deliver synthesizable RTL for one or more RISC-V compliant IP blocks (e.g., Power Management, timer, interrupt controller, debug module, peripheral interfaces).

Implement new architectural features and microarchitectural optimizations

Analyze and resolve design bugs in functional simulations

Support RTL quality checks such as Lint, CDC, RDC, basic synthesis, Power Intent.

Support in automation of IP design flows

Participate in design reviews and maintain version-controlled deliverables.

Tenstorrent ,Bengaluru

Station Overview

Project 1

Details Awaited

Project 2

RISC-V Design Verification Internship

Project 3

RTL Design Intern – RISC-V System IP